Traditional hard disk drive (HDD) read channels use a technique known as peak detection for extracting digital information from the analog information stored on the disk's magnetic surface. In this technique, the magnitude of the waveform is sampled during a sampling window, and if the waveform level is above a certain threshold, the data is considered a "one." Otherwise, the data is considered a "zero."
Using this technique of data encoding, each "one" requires a change in the direction of magnetization (known as a flux change) on the magnetic medium of the disk. The number of flux changes which can be accommodated in a given length of a data channel is limited by the magnetic properties of the recording medium on the disk. This places an upper limit on the density of data which can be stored on the disk.
More recently, advanced encoding techniques utilizing discrete time signal processing (DTSP) have been used to improve the density of data on a hard disk. One family of codes in common use are known as Run Length Limited (RLL) codes. RLL codes encode information in the length of the "run" of zeros between each one. RLL codes therefore reduce the number of flux changes required to convey a given amount of information. By increasing the amount of data conveyed per flux change, RLL codes allow data to be stored with greater density on magnetic disks.
Since the sequence of bits written to a disk using an RLL code is not the same as the bit sequence which is intended to be read, the data must be decoded during the read process to recover the original data bit stream. Some data encoding/decoding systems known in the prior art include partial response, maximum likelihood (PRML); extended PRML (EPRML); enhanced, extended PRML (EEPRML); fixed delay tree search (FDTS); and decision feedback equalization (DFE).
Several of these systems require maximum likelihood detection for the data signal sampled during each clock cycle. This maximum likelihood detection is usually performed by a Viterbi detector. A Viterbi detector is a device which implements the Viterbi algorithm, named after Andrew Viterbi, who developed the algorithm in 1967. Viterbi detectors generally are well-known in the prior art.
In particular, the operating principles of an analog Viterbi detector for decoding rate-8/9 partial response type IV (PR4) signals are discussed in the prior art. See, e.g., Thomas W. Matthews and Richard R. Spencer, An Integrated Analog CMOS Viterbi Detector for Digital Magnetic Recording, 28 IEEE Journal of Solid-State Circuits 1294 (December 1993). For each sampled data bit, this detector must calculate or measure a quantity known as a "metric." The Viterbi algorithm is applied to a series of such calculated metrics to produce a decoded data bit stream.
Calculation of the metric for an input signal sampled during one clock cycle requires a comparison of the input signal V.sub.IN with a high reference voltage V.sub.REF+, a low reference voltage V.sub.REF-, and the metric from the previous clock cycle. More specifically, the output metric V.sub.M for clock cycle n should be determined according to the following rules: EQU If (V.sub.IN -V.sub.REF+)&gt;V.sub.M(n-1) then V.sub.M(n) =(V.sub.IN -V.sub.REF+) (1) EQU If (V.sub.IN -V.sub.REF-)&lt;V.sub.M(n-1) then V.sub.M(n) =(V.sub.IN -V.sub.REF-) (2) EQU If (V.sub.IN -V.sub.REF-)&gt;V.sub.M(n-1) &gt;(V.sub.IN -V.sub.REF+) then V.sub.M(n) =V.sub.M(n-1) ( 3)
A method and circuit for reliably and accurately implementing these rules to calculate a metric in a Viterbi detector is needed.
A prior art circuit utilized a sample-and-hold circuit to sample the voltage on an output node every clock cycle. Under the conditions of rules (1) and (2), one of which occurs whenever a one is read from the disk, the output from an appropriate summing amplifier would be switched to the input of the sample-and-hold circuit during the sample mode. At the sample-to-hold mode transition, the sample-and-hold circuit input would be transferred to the sample-and-hold circuit output node.
Under the condition of rule (3), which occurs when a zero is read from the disk, all switches between the summing amplifiers and the sample-and-hold circuit would be left open. The sample-and-hold circuit would resample and transfer to its output node the same input voltage every clock cycle. The voltage on the output node would thus remain substantially unchanged from the previous clock cycle, as required by rule (3).
Unfortunately, the act of sampling the input voltage alters that voltage slightly due to gain error and clock feedthrough in the sample-and-hold circuit. Moreover, if zeros are encountered for several consecutive clock cycles, the deviations in the sample-and-hold output voltage are compounded by sampling the input voltage every clock cycle. This introduces error into the calculation of the metric, which in turn renders the results of the Viterbi algorithm calculations inaccurate. As a result, errors may be introduced into the data decoding process. Therefore, a method and circuit for more accurately implementing rules (1)-(3) to calculate a metric in a Viterbi detector are needed.